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PRELIMINARY DATA SHEET
SDA 9488X PIP IV Basic SDA 9588X OCTOPUS Cost-effective Picture-In-Picture ICs
Edition Feb. 28, 2001 6251-561-1PD
SDA 9488X SDA 9588X
Preliminary Data Sheet
Cost effective Picture-In-Picture (PIP) ICs
Version 1.3 General Description SDA 9488X 'PIP IV Basic' and SDA 9588X 'OCTOPUS' belong to a new generation of costeffective PiP processors that combine high-quality digital PIP signal processing, digital multistandard color decoding and AD/DA conversion on a single chip. Both devices are equipped with CVBS and Y/C input interfaces. In addition the SDA 9588X is also able to process YUV input signals for displaying high-quality video signals e.g. coming from a DVD source.
CMOS
P-DSO28-1
Figure 0-1
Picture-In-Picture
The integrated digital color decoder is able to decode all analog TV standards (PAL, NTSC and SECAM) and detects the standard automatically. Therefore the IC is suited for world-wide use. A picture reduction from 1/9 to 1/81 of original size selectable in fine steps is possible. The transfer functions of the decimation filters are optimally matched to the selected picture size reduction and can furthermore be adjusted to the viewer's requirements by a selectable peaking. A maximum of 216 luminance and 2x54 chrominance pixels per line are stored in the memory. Type SDA 9488X SDA 9588X Micronas Package P-DSO28-1 P-DSO28-1 -2
SDA 9488X SDA 9588X
Preliminary Data Sheet
1 2 3 4 4.1 4.1.1 4.1.2 4.1.3 4.1.4 4.2 4.3 4.4 4.5 4.6 4.6.1 4.6.2 4.6.3 4.7 4.7.1 4.7.2 4.7.3 4.8 4.8.1 4.8.2 4.8.3 4.8.4 4.8.5 4.8.6 4.9 4.9.1 4.9.2 4.10 4.10.1 4.10.2 4.10.3 4.10.4 5 6 6.1 6.2 Micronas
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Analog Frontend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 AD-Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Automatic Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Signal Magnitudes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Inset Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Chroma Decoding And Standard Search . . . . . . . . . . . . . . . . . . . . . . . . . .13 Comb Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Luminance Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Single PIP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Horizontal And Vertical Fine Positioning . . . . . . . . . . . . . . . . . . . . . . . . .19 Multi Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Display Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Mixed Standard Applications And (S)VGA Support . . . . . . . . . . . . . . . . .23 Display standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Picture Positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Output Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Luminance Peaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 RGB Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Framing And Colored Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 16:9 Inset Picture Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Parent Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Select Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 DA-Conversion And RGB / YUV Switch . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Contrast, Brightness and Peak Level Adjustment . . . . . . . . . . . . . . . . . .32 Pedestal Level Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Closed Caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Widescreen Signalling (WSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Indication Of New Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Violence Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 I2C Bus Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 I2C-Bus Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 -3
SDA 9488X SDA 9588X
Preliminary Data Sheet
6.3 6.4 7 8 9 10 11 12
I2C bus Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 I2C Bus Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Recommended Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Micronas
-4
SDA 9488X SDA 9588X
Preliminary Data Sheet Features
1
Features
* Single chip solution: - AD-conversion for CVBS or Y/C or YUV1), multistandard color decoding, PLL for synchronization of inset channel, decimation filtering, embedded memory, RGBmatrix, DA-conversion, RGB/YUV switch, data-slicer and clock generation integrated on chip * Analog inputs: - 3x CVBS or 1x CVBS and 1x Y/C or 1xYUV (SDA 9588X) alternatively - Clamping of each input - All ADCs with 8 bit amplitude resolution - Automatic Gain Control (AGC) for Y and CVBS * Inset Synchronization: - Multiple time constants for reliable synchronization - Automatic recognition of 625 lines / 525 lines standard * Color Decoder: - PAL-B/G, PAL-M, PAL-N(Argentina), PAL60, NTSC-M, NTSC4.4 and SECAM - Adjustable color saturation - Hue control for NTSC - Automatic Chroma Control (-24 dB ... +6 dB) - Automatic recognition of chroma standards: different search strategies selectable - Single crystal for all standards - IF-characteristic compensation filter * Decimation: - PIP sizes between 1/81 and 1/9 adjustable with steps of 2 lines and 4 pixel - Resolution up to 216 luminance and 2x54 chrominance pixels per inset line - Horizontal and vertical filtering dependent on picture size * Display Features: - 7 bit per pixel stored in memory - Field and joint-line free frame mode display - Display on VGA and SVGA screen (fH limited to 40kHz) - 8 different read frequencies for 16:9 compatibility - Line doubling mode for progressive scan applications - Freeze picture - Coarse positioning at 4 corners of the parent picture - Fine positioning at steps of 4 pixels and 2 lines * Output signal processing: - 7 Bit DAC - RGB or YUV switch: insertion of an external source without PIP processing - Digital interpolation for anti-imaging
1)
available with SDA 9588X only 1-5
Micronas
SDA 9488X SDA 9588X
Preliminary Data Sheet Features
*
* * * * * *
- Adjustable transient improvement for luma (peaking) - Contrast, Brightness and Pedestal Level adjustable - Analog outputs: Y, +(B-Y), +(R-Y), or Y, -(B-Y), -(R-Y) or RGB - Three RGB matrices available: NTSC(Japan), NTSC(USA) or EBU - 64 different background colors and 4096 different frame colors - Plain or 3D frame with variable width and height Data Slicing: - Slicing of closed-caption (CC) or wide-screen-signaling (WSS) data - Violence blocking capability (V-chip) - Several filter for XDS data extraction I2C-Bus control (400 kHz) High stability clock generation PDSO 28-1 package (SMD) Full SDA 9489X and SDA 9589X upward compatibility SDA 9388X / SDA 9389X pinout compatibility 3.3V supply voltage (5V input capable)
Micronas
1-6
SDA 9488X SDA 9588X
Preliminary Data Sheet Pin Configuration
2
Pin Configuration
XIN XQ HSP VSP SDA SCL VDD VSS I2C INT IN1 IN2 IN3 FSW
1 2 3
28 27 26
CVBS1 VREFM CVBS2 VREFL CVBS3 VSSA1 VDDA1 VREFH VSSA2 VDDA2 OUT1 OUT2 OUT3 SEL
PDSO 28 -1
4 5 6 7 8 9 10 11 12 13 14
25 24 23 22 21 20 19 18 17 16 15
Figure 2-1
Pinning
Figure 2-2
Package Outlines
Micronas
2-7
SDA 9488X SDA 9588X
Preliminary Data Sheet Pin Configuration
Numb er 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Name XIN XQ HSP VSP SDA SCL VDD VSS I2C INT IN1 IN2 IN3 FSW SEL OUT3 OUT2 OUT1 VDDA2 VSSA2 VREFH VDDA1 VSSA1 CVBS3 VREFL CVBS2 VREFM CVBS1
Type I O I/TTL I/TTL I/O I S S I O/TTL I/ana I/ana I/ana I O O/ana O/ana O/ana S S I/ana S S I/ana I/O I/ana I/O I/ana
Description crystal oscillator (input) or external clock input crystal oscillator (output) horizontal sync for parent channel vertical sync for parent channel I2C-bus data I2C-bus clock digital supply voltage digital ground I2C Address interrupt V/R input for external YUV/RGB source Y/G input for external YUV/RGB source U/B input for external YUV/RGB source fast switch input for YUV/RGB switch fast blanking output for PIP analog output: chrominance signal +(B-Y) or -(B-Y) or B analog output: luminance signal Y or G analog output: chrominance signal +(R-Y) or -(R-Y) or R analog supply voltage for DAC analog ground for DAC uppper reference voltage for ADC and DAC analog supply voltage for ADC analog ground for ADC CVBS3 or V (SDA 9588X) or C Input lower reference voltage for ADC CVBS2 or U (SDA 9588X) or Y (of Y/C) Input mid-level reference voltage for ADC CVBS1 or Y (of YUV, SDA 9588X) Input
I= Input / ana=analog / O= Output / TTL=Digital (TTL) / S=Supply voltage
Table 2-1 Micronas
Pin Description 2-8
3
SDA 9588X
SDA 9488X
Micronas
VDD
7 8 19 20
Figure 3-1
VSS VDDA2VSSA2
VDDA1 VSSA1
22
23
VREFH
MUX DEMUX
27
VREFM 3x7bit
21
Block Diagram
Block Diagram
Skewcomp. H/V Scaler Decimation RGB Matrix Triple DAC Peaking Oversampling Insertion
VREFL
25
TRIPLE ADC 3x8bit 1)
eDRAM
Color Decoder
PAL/ SECAM/ NTSC
11
IN1
12 13 14
DUV/DCHR
DCVBS/DY
Frame Generation 512kbit
IN2 IN3
CVBS1
28
3-9
Memory Controller Display Controller Inset Sync Processing Data Slicer Acquisition
10 1 2
CVBS2
26
CVBS3
24
Input Select Clamp Gain
Fast FSW RGB/YUV 18 OUT1 Switch 17 OUT2
16 15
Y/C and Sync Sep.
OUT3 SEL
I2C Controller Clock Synthesizer
Parent Sync Processing
3 4
6
5
9
SCL
SDA
I2C
INTR
XIN
XQ
HSP
VSP
1) SDA9588X, SDA 9488X: 2x8bit
Preliminary Data Sheet
Block Diagram
XTAL 20.25 MHz
SDA 9488X SDA 9588X
Preliminary Data Sheet System Description
4 4.1 4.1.1
System Description Analog Frontend Input Selection
An analog inset CVBS signal can be fed to the inputs CVBS1-3 of SDA 9588X resp. SDA 9488X. Each of these sources is selectable via I2C bus (CVBSEL). CVBS2 and CVBS3 can be used as separate Y/C inputs. YUV sources can be connected to CVBS1, CVBS2 and CVBS3 provided YUV operation at the SDA 9588X being enabled (YUVSEL). Using an external switch the SDA 9588X can operate in applications with both YUV and CVBS signals.
CVBSEL D1 D0
YUVSEL
Input
remark
CVBS1 0 0 0 0 1 Y (VBS) CVBS
CVBS2 CVBS Y (VBS) U (CB)
CVBS3
0 0 1 1 X
0 1 0 1 X
C CVBS V (CR)
Y/C mode YUV mode (SDA 9588X only)
Table 4-1 4.1.2
Input selection
AD-Conversion
All signal are clamped and AD-converted with an amplitude resolution of 8bit. CVBS and Y signals are clamped to the sync bottom whereas U/V and C signals are clamped to their mid-level during blanking.
Inset Video
HD
CLMPIST
CLAMPI
CLMPID
Figure 4-1 Micronas
Clamping timing 4-10
SDA 9488X SDA 9588X
Preliminary Data Sheet System Description
The clamping pulse can be shifted in position (CLMPIST) and length (CLMPID) to adjust to the specific application. The ADCs are driven by a 20.25 MHz free running crystal clock which is not related to the incoming CVBS signal. To avoid aliasing by subsampling the CVBS signal and the Y/C signals should be bandlimited to 10MHz. In the same manner the U/V signal frequency spectrum (SDA 9588X) should not exceed 5 MHz. The digital filtering suppresses all frequencies above the useable spectrum. 4.1.3 Automatic Gain Control
To accommodate to different CVBS input voltages an automatic gain control has been implemented. The chip works correctly for input voltages in the range from 0.5 to 1.5Vpp. For best signal-to-noise ratio, the maximum CVBS amplitude is recommended if available. The AGC behavior can be chosen out of four possibilities (AGCMDE): The sync height serves as reference for the gain control in the typical application. When using overflow detection only, the gain is set to maximum and is reduced whenever an overflow occurs. This procedure will be executed again when a channel change is detected or the gain control is manually reset by AGCRES.
2
Automatic Gain Control Characteristic
1.5 Input Voltage [V]
1
0.5
0
0
2
4
6
8 AGCVAL
10
12
14
16
Figure 4-2 4.1.4
AGC characteristic Signal Magnitudes
The nominal CVBS signal with 75% color has a magnitude of 1 Vpp. The upper headroom is left to permit signals with 100% color resulting in 1.23 Vpp. The Y signal must always contain the sync part. Its levels correspond to the CVBS levels except for the missing color and burst. After A/D conversion the video part is clamped to its black value and is amplified to 224 digital steps. The nominal signal levels ensure correct brightness and saturation. The YUV signal levels conform to the ITU 601 recommendation.
Micronas
4-11
SDA 9488X SDA 9588X
Preliminary Data Sheet System Description
255 217
upper headroom
255 224 CRYC = 1.2 Vpp white
upper headroom
SRC = 0.89 Vpp
SRUV = 0.7 Vpp
SRY = 1 Vpp
128
68 4 0
burst
black
32
lower headroom
0
lower headroom
Figure 4-3
255 240 212
CVBS/Y and chroma ADC input signal range
255 240 212 CRUV = 0.8 Vpp SRUV = 0.7 Vpp 75% V 128
upper headroom
upper headroom
75% U 128
44 16 0
lower headroom
44 16 0
lower headroom
Figure 4-4
UV input signal range
Conversion Range CRYC Signal Range SRY Signal Range SRC Conversion Range CRUV Signal Range SRUV
AGCVAL D3 D2 D1 D0
0 1 1
0 0 1
0 0 1
0 ... 0 ... 1
0.5Vpp ... 1.2Vpp ... 1.5Vpp
0.42Vpp ... 1.0Vpp ... 1.25Vpp 0.89Vpp 0.8Vpp 0.7Vpp
Table 4-2 Micronas
ADC conversion range and required input signal voltage 4-12
CRUV = 0.8 Vpp
CRYC = 1.2 Vpp
100% chroma
75% chroma
burst
SDA 9488X SDA 9588X
Preliminary Data Sheet System Description
4.2
Inset Synchronization
Horizontal and vertical sync pulses are separated after elimination of the high frequency components of the CVBS signal by a low pass filter. Horizontal sync pulses are generated by a digital phase-locked-loop (DPLL). Its time constant is adjustable between fast and slow behavior in four steps (PLLITC) to consider different input sources (e.g. VCR). Noisy input signals become more stable when a noise-reduction is enabled (NSRED). Additionally weak input signals from a satellite dish ('fishes') become more stable when SATNR is enabled. Both should be enabled to have best available performance. When NOSIGB is enabled, a colored background is shown instead of the picture when PIP is out of synchronization. The detected line standard is indicated by SYNCSTAT. 4.3 Chroma Decoding And Standard Search
The system is able to decode NTSC and PAL signals with a subcarrier of 3.58MHz and 4.43MHz (PAL B/M/N/60, NTSC M/4.4) as well as SECAM signals with 4.05/4.2MHz subcarrier. The system may be forced to a certain standard, or an automatic standard detection can be used (CSTAND). For automatic standard detection, some standards which are not likely to be received can be ignored to improve the detection process. Depending on the detected line standard (525 or 625 lines) the color standard detection circuit searches for 60 Hz signals (NTSC-M / PAL-M / PAL 60 / NTSC44) or 50 Hz signals (PAL-B / SECAM / PAL-N) respectively. Within each line standard, the standard is detected by consequently switching from one to another. This standard detection process can be set to medium or fast behavior (LOCKSP). In medium behavior 30 fields (in fast 20) are used to detect the standard. If not being successful within this time period the system tries to detect another one. For SECAM detection, a choice between two recognition levels is possible (SCMIDL) and the evaluated burstposition is selectable (BGPOS). .
CSTANDEX D1 D0 NTSCM PAL60 PAL-N PAL-M PAL-B SECAM NTSC 44
0 0 1 1 Table 4-3
0 .1 0 1 Considered color standards for automatic standard detection
For getting the chrominance information the digitized video signal is multiplied with the regenerated color subcarrier once in-phase and once phase-shifted by 90. After lowpass filtering digital UV is available for PAL and NTSC. The subcarrier is regenerated Micronas 4-13
SDA 9488X SDA 9588X
Preliminary Data Sheet System Description
by a digital PLL. At SECAM operation the PLL runs free and generates the line-wise alternating subcarriers. A CORDIC structure demodulates the frequency-modulated UV signals. The following SECAM de-emphasis filter characteristic is adjustable (DEEMP). The chroma signal can be filtered before demodulation by means of a selectable IFprefilter (IFCOMP).
0
5 2.5
3.58
4.4
5
0
IFCOMP = '00' IFCOMP = '01'
gain [dB]
10
DEEMP = '00' DEEMP = '01' DEEMP = '10' DEEMP = '11'
gain [dB]
2.5 5 7.5
IFCOMP = '10'
15
20
0
0.5
1
1.5
2
2.5
10
2
3
4 frequency [MHz]
5
6
frequency [MHz]
Figure 4-5
SECAM de-emphasis filter characteristic and IF-compensation filter characteristic
The Hue Control (HUE) influences the phase of the demodulation subcarrier between -44.8 and 43.4 in steps of 1.4. This is provided for NTSC only and adjustment is ineffective for PAL and SECAM signals. The reference for the subcarrier generation is a crystal stable clock of 20.25000 MHz. In order to avoid color standard detection problems, the maximum deviation of this frequency should not exceed 100ppm. For a good PLL locking behavior a maximum deviation of 40ppm is recommended. A small frequency adjustment (-150 ... +310 ppm) is possible for using a crystal with small frequency deviations (SCADJ). For test purposes, CPLL allows to open the loop of the chroma PLL. For deviations in the chroma signal up to 30dB, a stable output amplitude after chroma decoding is achieved due to the ACC (Automatic Chroma Control). If the chroma signal (color burst) is below a selectable threshold (CKILL), the color will be switched off. Alternatively the color-killer can be bypassed and the color can be switched on or off under all conditions (COLON). By setting ACCFIX, the automatic chroma control is disabled and set to a default value.
Micronas
4-14
SDA 9488X SDA 9588X
Preliminary Data Sheet System Description
CKILL D1 0 0 1 1 X Table 4-4 D0 0 1 1 1 X
COLON 0 0 0 0 1
color killed at damping of 30 dB 18 dB 24 dB color always off color always on
Color-killer adjustment
The bandwidth of the chroma filter is adjustable via CHRBW. The bandwidth depends on whether the decoder is in SECAM operation or not. A change in CHRBW does not result in a chrominance position shift on the screen. CKSTAT can be read out and gives information whether the color is switched on or off. STDET indicates the detected color standard. Additionally PALID signals whether a PAL signal or a NTSC signal is applied. 4.4 Comb Filtering
Depending on the selected picture size and color standard, a comb filtering is performed for luminance and chrominance. A comb filter uses the spectral interleaving of the encoded luminance and chrominance to separate both without cross artifacts. Thus cross-color and cross-luminance are suppressed effectively. For NTSC sources, a comb filtering is performed for all picture sizes. Due to reduced bandwidth in horizontal and vertical direction a strong reduction of cross artifacts can be achieved for PAL signals. The same applies for the luminance signal of SECAM signals. 4.5 Luminance Processing
The A/D-converted CVBS (or Y) signal is digitally clamped to back porch. Depending on the transmitted standard and operational area, an offset between black- and blanking level can be found in the incoming signal ('7.5 IRE'). As for some applications a black offset is not desired, controlling may be done using LMOFST. The positive or negative offset is added to the Y signal before scaling.
Micronas
4-15
SDA 9488X SDA 9588X
Preliminary Data Sheet System Description
Received signal
BLACK value BLANK value
Processed signal
BLACK value BLANK value
M standard signals
LMOFST='00' (no additional offset)
LMOFST='10' (reduction of 16 LSB)
BLACK value BLANK value
BLACK value BLANK value
B/G/H/I/N standard signals
LMOFST='00' (no additional offset)
LMOFST='01' (addition of 16 LSB)
Figure 4-6
Black level correction of luminance signal
The color carrier is removed out of a CVBS signal by means of a notch filter. It is set to the corresponding color carrier (3.58 or 4.4 MHz) only if the standard is detected permanently. This prevents the luminance sharpness of being changed within the standard search process. For Y signals the notch is disabled. For a fine adjustment of delaycompensation between luminance and chrominance, YCDEL allows a luminance shifting in 16 steps of 50ns. 4.6 4.6.1 Decimation Single PIP Mode
Luminance and chrominance signals are filtered in horizontal and vertical direction. The coarse horizontal and vertical picture size (1/3, 1/4, 1/6) is independently programmable with SIZEHOR and SIZEVER. A fine adjustment in steps of 4 pixel and 2 lines is possible by HSHRINK and VSHRINK, which allows correct aspect ratio for multistandard applications (50/60 Hz mixed mode, (S)VGA). For main decimation factors, the stored number of pixel and lines are listed in the following tables.
Micronas
4-16
SDA 9488X SDA 9588X
Preliminary Data Sheet System Description
SIZEHOR D1 0 0 1 1
1)
D0 0 1 0 1
horizontal scaling 3:11) 3:1 4:1 6:1
PIP Pixel per line Y 216 216 160 108 (B-Y) 54 54 40 27 (R-Y) 54 54 40 27
only used for compatiblity with other SDA 948xX/958xX types Number of stored pixel per line dependent on SIZEHOR
Table 4-5
SIZEVER D1 0 0 1 1
1)
vertical scaling
PIP lines 625 lines source 525 lines source 72 72 54 36
D0 01) 1 0 1 3:1 3:1 4:1 6:1
88 88 66 44
only used for compatibility with other SDA 948xX/958xX types Number of stored lines per field
Table 4-6
Micronas
4-17
SDA 9488X SDA 9588X
Preliminary Data Sheet System Description
0 1 2 3 4 5 6 7 8 9 10 11 12 13 0 1 2 3 4 5 6 7 8 9 10 11 12
1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2
3,00 3,04 3,11 3,17 3,23 3,29 3,37 3,44 3,51 3,60 3,67 3,76 3,84 3,94 4,05 4,16 4,27 4,38 4,50 4,63 4,77 4,91 5,06 5,22 5,41 5,59 5,78
216 212 208 204 200 196 192 188 184 180 176 172 168 164 160 156 152 148 144 140 136 132 128 124 120 116 112
0 1 2 3 4 5 6 7 8 9 10 11 12
3 3 3 3 3 3 3 3 3 3 3 3 3
6,00 6,23 6,48 6,75 7,04 7,35 7,70 8,10 8,52 8,99 9,51 10,12 10,64
108 104 100 96 92 88 84 80 76 72 68 64 60
Table 4-7
Number of stored pixel per line dependent on HSHRNK
Micronas
4-18
SDA 9488X SDA 9588X
Preliminary Data Sheet System Description
625 lines
525 lines
625 lines
525 lines
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2
3,00 3,07 3,14 3,21 3,30 3,38 3,47 3,56 3,66 3,77 3,89 4,00 4,13 4,25 4,41 4,56 4,72 4,88 5,06 5,28 5,50 5,75
88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 48 46
3 3,09 3,19 3,28 3,38 3,49 3,61 3,73 3,87
72 70 68 66 64 62 60 58 56
0 1 2 3 4 5 6 7 8 9 10
3 3 3 3 3 3 3 3 3 3 3
6,00 6,28 6,61 6,94 7,31 7,78 8,25 8,81 9,42 10,17 11,02
44 6,00 42 6,38 40 6,75 38 7,22 36 7,73 34 8,30 32 9,00 30 9,80 28 10,78 26 24
36 34 32 30 28 26 24 22 20
4,01 4,15 4,31 4,5 4,69 4,9 5,13 5,39 5,7
54 52 50 48 46 44 42 40 38
Table 4-8 4.6.2
Number of stored lines per field dependent on VSHRNK Horizontal And Vertical Fine Positioning
All picture sizes are pre-centered inside the frame. In addition, if necessary the vertical and horizontal acquisition area can be shifted by VFP for vertical and HFP for horizontal direction. 4.6.3 Multi Display Mode
SDA 9488X and SDA 9588X offer the feature to display a sub-picture more than once. The picture size and arrangement depends on the display mode (DISPMOD) and not on SIZEHOR or SIZEVER. Hence variable scaling is not possible in these modes.
Micronas
4-19
SDA 9488X SDA 9588X
Preliminary Data Sheet System Description
Display Mode 1
DISPMOD D1 0 D0 0
Size SIZEHOR/ SIZEVER HSRHNK/ VSHRNK 3 X1/9 4 X 1/16
Picture configuration single PIP mode,
Pixel 216 60 88 24
Lines 625 525 72 20
2 3
0 1
1 0
one upon another (same content) one upon another (same content)
216 156
264 264
216 216
Table 4-9
Multi-display modes
The display modes are shown in the appendix. The sizes of the partial pictures are listed in table 4-9. 4.7 Display Control
The on-chip memory capacity is 512 kbits. Provided that the same standard (50 or 60 Hz) video sources are applied to inset and parent channel, jointline-free frame mode display is possible. This means that every incoming field is processed and displayed by the SDA 9488X/SDA 9588X processor. The result is a high vertical and time resolution. For this purpose the standard is analyzed internally and frame mode display is blocked automatically, if the described restrictions are not fulfilled. Then only every second incoming field is shown (field mode). Field mode normally shows jointlines. This is caused by an update of the memory during read out. The result is that one part of the picture contains new picture information and the other part contains one earlier written field. The switching from or to frame mode is free of artifacts. Activation of frame-mode display is blocked automatically if at least one of the following conditions is not fulfilled: * Inset and parent channel have the same field repetition frequency. This means that frame mode is possible only for 50Hz inset and parent sources or 60Hz inset and parent sources. * Interlace signal is detected for inset and parent channel. For progressive scan or (S)VGA display therefore only field mode is possible. For some VCRs in trick mode, often no interlace is detected also. * The number of lines is within a predefined range for inset (FMACTI) or parent (FMACTP) channel (assuming standard signals according to ITU)
Micronas
4-20
SDA 9488X SDA 9588X
Preliminary Data Sheet System Description
FMACTP 0 1 0 1 Table 4-10
parent standard 50 Hz 50 Hz 60 Hz 60 Hz
number of lines per field 310...315 290...325 260...265 250...275
FMACTI 0 1 0 1
inset standard 50 Hz 50 Hz 60 Hz 60 Hz
number of lines per field 310...315 290...325 260...265 250...275
Required number of lines for frame mode display
The system may be forced to field mode by means of FIESEL. Either first or second field is selectable. 'One of both' takes every second field independent of the field number. This is meant for sources generating only one field (e.g. video-games). For progressive scan conversion systems and HDTV / (S)VGA displays a line doubling mode is available (PROGEN). Every line of the inset picture is read twice. Memory writing is stopped by FREEZE bit. The field stored in the memory is then continuously read. As the picture decimation is done before storing, the picture size of a frozen picture can not be changed. Depending on the phase between inset and parent signals a correction of the display raster for the read out data is performed. Synchronization of memory reading with the parent channel is achieved by processing the parent horizontal and vertical synchronization signals. Horizontal and vertical pulses may be provided. The signals are fed to the IC at pin HSP for horizontal synchronization and pin VSP for vertical synchronization. HSPINV or VSPINV respectively allow an inversion of the expected signal polarity.
HSP VSP
VSPDEL VSPDEL max=151 (75) s field 1 window
VSPD
(internal)
field 0 window tH/2 = 32 (16) s tH = 64 (32) s
values in brackets () apply for 100Hz systems
Figure 4-7 Micronas
Field detection and phase adjustment of vertical pulse (VSP) 4-21
SDA 9488X SDA 9588X
Preliminary Data Sheet System Description
As the external VSP and HSP signals may come from different devices with different delay paths, the phase between V-sync and H-sync is adjustable (VSPDEL). An incorrect setting of VSPDEL may result in wrong or unreliable field detection of parent channel. Normally a noise reduction of the incoming parent vertical pulse is performed. With this function missing vertical pulses are compensated. The circuit works for 50/60 Hz applications as well as progressive and 100/120Hz application. (S)VGA signals are supposed to be very stable and therefore not supported by the noise suppression. By means of VSPNSRQ, vertical noise suppression is switched off. A great variety of combinations of inset and parent frequencies are possible. The following table shows some constellations:
Inset Parent frame correct aspect correct aspect vertical 1) 1) Frequency Frequency mode ratio ratio noise (HSP/VSP) (single pip) (multi display) suppression selectable
50 50 60 60 50 50 60 60 50 50 60 60 50 60
1) 2)
50i 60i 50i 60i 50p 60p 50p 60p 100i 120i 100i 120i (S)VGA (S)VGA
2)
2)
standard signals supposed valid for some parent frequencies. Please refer to Chapter 4.7.1 Available Features with varying inset and parent standards
Table 4-11
Micronas
4-22
SDA 9488X SDA 9588X
Preliminary Data Sheet System Description
4.7.1
Mixed Standard Applications And (S)VGA Support
fH (kHz) TH (s) THact( s) lines/ active fdot (MHz) scan correct aspect ratio
remark (Napel X Naline @ fV)
720X576@50Hz (TV) 702X488@60Hz (TV) 720X576@100Hz (TV 100 Hz) 702X488@120Hz (TV 120 Hz) 720X576@50Hz (TV progressive) 702X488@60Hz (TV progressive) 640X480@60Hz (VGA) 640X480@72Hz (VGA) 640X480@75Hz (VGA) 800X600@56Hz (SVGA) 800X600@60Hz (SVGA) 800X600@72Hz (SVGA) 800X600@75Hz (SVGA) 800X600@85Hz (SVGA) 1024X768@43Hz (SVGA) Table 4-12 Micronas
15.6 15.7 31.2 31.2 31.2 31.2 31.5 37.9 37.5 35.2 37.9 48.1 46.9 53.7 35.5
64.0 63.6 32.0 31.8 32.0 31.8 31.8 26.4 26.7 28.4 26.4 20.8 21.3 18.6 28.2
52.0 52.7 26.0 26.4 26.0 26.4 25.4 20.3 20.3 22.2 20.0 16.0 16.2 14.2 22.8
625/ 576 525/ 488 625/ 576 525/ 488 625/ 576 525/ 488 525/ 480 520/ 480 500/ 480 625/ 600 625/ 600 666/ 600 625/ 600 631/ 600 817/ 768
13.5 13.5 27 27 27 27 25.2 31.5 31.5 36.0 40.0 50.0 49.5 56.3 44.9
interlace interlace interlace interlace progressive progressive progressive progressive progressive progressive progressive progressive progressive progressive interlace
Examples of supported parent signals 4-23
SDA 9488X SDA 9588X
Preliminary Data Sheet System Description
The SDA 9488X resp. SDA 9588X allow multiple scan rates for the use in desktop video applications, VGA compatible or 100Hz TV sets. All features are provided in 'normal' operating modes at auto detected 50Hz and 60 Hz parent and inset standards. 2fH modes (100/120Hz and progressive) are supported by line frequency- and pixel clock doubling and are not detected automatically. Even on a 16:9 picture tube correct aspect ratio can be displayed by selecting the approbiate parent clock. The video synthesizer generates also a special pixel clock for VGA display (see chapter 5.5.9 for details). As (S)VGA consists of a variety of scan rates the correct aspect ratio is not adjustable for all modes with the parent clock (HZOOM) because of the limited count of frequencies. For single PIP only, correct aspect ratio is maintained by the vertical and horizontal scaler (HSHRINK and VSHRINK). It is possible to display (S)VGA sources for parent display, as long as the horizontal frequency is lower than 40 kHz and the signal does not contain more than 1023 lines. For progressive scan mode, PROGEN must be set. Additionally field-mode should be forced to prevent unallowed frame-mode displaying (FIESEL). As the (S)VGA normally does not fit to the display raster generated in the vertical noise suppression, VSPNSRQ should be disabled. (S)VGA signals for inset channel are not supported. PROGEN 0 0 1 1 Table 4-13 4.7.2 READD 0 1 0 1 Expected input signal 50 or 60 Hz signal interlace 100 or 120 Hz signals interlace (reserved) 50 or 60 Hz or (S)VGA signal progressive
Selection of display field repetition Display standard
For a single-PiP, the number of displayed lines depends on the selected picture size and on the signal standard. For multi picture display, the number of displayed lines depends on the selected picture size and on the signal standard of the parent signal. Additionally, a standard can be forced by DISPSTD.
Micronas
4-24
SDA 9488X SDA 9588X
Preliminary Data Sheet System Description
DISPSTD D1 0 0 0 1 1 D0 0 0 1 0 1
DISPMOD 0 >0 x x x
Display Standard PIP depends on detected inset standard (single pip) PIP depends on detected parent standard (multi display) PIP display is always in 625 lines mode PIP display is always in 525 lines mode freeze last detected display standard and size
Table 4-14
Display standard selection
If a 625 lines picture is shown with a 525 lines parent signal, some lines are missing on top and bottom of picture. If a 525 lines picture is shown with a 625 lines display standard, missing lines at top and bottom are filled with background color. 4.7.3 Picture Positioning
The display position of the inset picture is programmable to the 4 corners of the parent picture (CPOS). From there PIP can be moved to the middle of the TV Picture with POSHOR and POSVER. The corner positions can be centered coarsely on the screen with POSOFH and POSOFV. Depending on coarse position, one PIP corner remains stable when changing the picture size. CPOS D1 0 0 1 1 D0 0 1 0 1 Coarse Position upper left upper right lower left lower right Reference corner of PiP upper left upper right lower left lower right increasing POSVER down down up up increasing POSHOR right left right left
Table 4-15
Coarse Positioning
Starting at every coarse position, the picture is movable to 256 horizontal locations (4 pixel increments) and 256 vertical locations (2 line increments). The pixel width on the screen depends on the selected HZOOM factor. Even POP-positions (Picture Outside Picture) in 16:9 applications are possible.
Micronas
4-25
SDA 9488X SDA 9588X
Preliminary Data Sheet System Description
POSHOR
CPOS='01' CPOS='00'
POSVER POSVER
CPOS='10'
POSHOR
CPOS='11'
Figure 4-8 4.8 4.8.1
Coarse Positioning Output Signal Processing Luminance Peaking
To improve picture sharpness, a peaking filter which amplifies higher frequencies of the input signal is implemented. The amount of peaking can be varied in seven steps by YPEAK. The setting '000' switches off the peaking. The value '011' is recommended. This provides a good compromise between sharpness impression and annoying aliasing. The characteristic for all possible settings is shown in fig. (4-9)
10 9 8 7 gain [dB] 6 5 4 3 2 1 0 0 0.1 0.2 0.3 0.4
YPEAK = '000' 0.5 YPEAK = '001' YPEAK = '111' YPEAK = '110' YPEAK = '101' YPEAK = '100' YPEAK = '011' YPEAK = '010'
normed frequency
Figure 4-9 Micronas
Characteristics of selectable peaking factors 4-26
SDA 9488X SDA 9588X
Preliminary Data Sheet System Description
Coring should be switched on by YCOR to reduce noise, which is also amplified when peaking is enabled. As the coring stage is in front of the peaking filter, 1 LSB noise will not be peaked. 4.8.2 RGB Matrix
The chip contains three different matrices, one suited for EBU standards, one suited for NTSC-Japan and one suited for NTSC-USA, which are selected via MAT. The signal OUTFOR switches between YUV output or RGB output. The signal UVPOLAR inverts the U and V channels and results in Y-U-V output. The standard magnitudes and angles of the color-difference signals in the UV-plane are defined as follows: MAT D1 0 0 1 1 D0 0 1 0 1 RGB matrices characteristics (B-Y) 2.028 2.028 2.028 Magnitudes (R-Y) 1.14 1.582 2.028 (G-Y) 0.7 0.608 0.608 (B-Y) 0 0 0 Angles (R-Y) 90 95 105 (G-Y) 236 240 250 EBU NTSC (Japan) NTSC (USA) (reserved) Standard
Table 4-16
The color saturation can be adjusted with SATADJ register in 16 steps between 0 and 1.875. Values above 1.0 may clip the chrominance signals. 4.8.3 Framing And Colored Background
Figure 4-10 Normal frame and 3D frame
Micronas
4-27
SDA 9488X SDA 9588X
Preliminary Data Sheet System Description
With FRSEL a colored frame is added to the inset picture. The chip can display two different types of frames, one simple monochrome frame and a more sophisticated frame giving a three dimensional impression. The frame elements are always placed outside the inset picture, except for the inner shade of three dimensional frame or inner frame in multipip-mode. There is no shift of the inset picture position if the inset frame width is modified. 4096 frame colors are programmable by FRY, FRU, and FRV, 4 bits for each component. Horizontal and vertical width of the frame are programmable independently by FRWIDH and FRWIDHV. If desired, frame color is displayed over the whole PIP size or whole picture size of the main channel when PIPBG is set accordingly.
PiP Picture background picture frame no frame color

shades no dark/light
background no background color frame color
Figure 4-11 Selectable picture configurations 64 background colors are programmable by BGY, BGU, BGV, 2 bits for each component. Alternatively BGFRC sets the background to frame color. 4.8.4 16:9 Inset Picture Support
To remove dark stripes at 16:9 inset pictures the vertical display area is reducable with VPSRED. The number of omitted lines depends on the vertical decimation factor.
Micronas
4-28

SDA 9488X SDA 9588X
Preliminary Data Sheet System Description
vertical decimation factor 1 ... 6
displayed lines (50Hz) 264 44
displayed lines (50Hz) with reduction 214 35
displayed lines (60Hz) 216 36
displayed lines (60Hz) with reduction 175 29
Figure 4-12 Number of lines without and with reduction of vertical picture size .
Figure 4-13 16:9 inset picture without and with reduction of vertical picture size 4.8.5 Parent Clock Generation
The phase of the output signals is locked to the rising edge of the horizontal sync pulse. The frequency varies in a certain range to ensure correct aspect ratio for 16:9 applications depending on HZOOM. The horizontal and vertical scaling can be used for all display frequencies. display format 4:3 4:3 16:9 16:9 Table 4-17 Micronas inset picture format 4:3 4:3 4:3 16:9 desired PiP format 4:3 16:9 4:3 16:9 required parent frequency 27 20.25 36 36 value of HZOOM D2 0 0 0 0 D1 0 0 1 1 D0 0 1 0 0
Format conversion using HZOOM 4-29
SDA 9488X SDA 9588X
Preliminary Data Sheet System Description
For variations of parental horizontal frequency (e.g. VCR), a digital correction of the position is useful to stabilize the picture (POSCOR). This circuit detects a varying parental line frequency and moves the picture to the place, where it would have been without this frequency deviation. The calculation is done once a field. 4.8.6 Select Signal
For controlling an external RGB or YUV switch a select signal is supplied. The delay of this signal is programmable for adaptation to different external output signal processing devices (SELDEL). SELDOWN sets this output to tristate (high-resistance).
frame
PiP signal OUTx
picture
SEL
SELDEL
Figure 4-14 Select timing 4.9 DA-Conversion And RGB / YUV Switch
The SDA 9588X/SDA 9488X include three 7bit DA-converters. Brightness (BRTADJ), Contrast (CON) and overall amplitude (PKLR, PKLG, PKLB) of the output signal are adjustable. External RGB or YUV signals can be connected to the inputs IN1...3. By forcing the FSW input to high-level these signals are switched to the outputs OUT1...3 while the internal signals are switched off. The FSW input signal is passed through to the SEL output. The setting of RGBINS determines wether an RGB insertion is possible and which source, the external picture or the PiP, gets priority.
Micronas
4-30
SDA 9488X SDA 9588X
Preliminary Data Sheet System Description
RGBINS='10' PIPON='1' OSD
R/V G/Y B/U
RGBINS='11' PIPON='1' OSD
RGBINS='00' PIPON='1'
RGBIN='1X' PIPON='0' OSD OSD
OSD
OSD
SEL
VDDA1
VREFM
VREFH
VDDA2
OUT1
OUT2 IN2
VREFL
CVBS1
CVBS2
CVBS3
VSSA1
PiP IV
VDD VSS I2C
VSSA2
OUT3 IN3
RGB/VYU
FSW
HSP
SDA
VSP
SCL
XIN
INT
IN1
XQ
SEL
FSW
OSD
OSD
Figure 4-15 Visualization of RGB/YUV insertion The external RGB or YUV signals are each clamped to the reference levels of the DACs to force uniform black levels in each channel. The clamping needs careful adjustment especially for VGA applications. The position and the length of the blanking pulse as well as the clamping pulse are adjustable (CLPPOS, CLPLEN). If READD is set to '1' (100Hz mode), all pulses are shortened by one half. HZOOM influences the adjustment range of the clamping and blanking pulse because of the modified clock frequency, but the pulse length is kept nearly constant.
Parent Video
HSP
allowed HSP range 256 T
BLANKP
a
b
CLAMPP
c
d
Figure 4-16 PIP horizontal blanking timing
Micronas
4-31
SDA 9488X SDA 9588X
Preliminary Data Sheet System Description
READD D2
CLPDEL D1 D0
CLPLEN D1 D0
a (s) Blanking Start
b (s) Blanking Duration
c (s) Clamping Start
d (s) Clamping Duration
0 0 0 0 1 1 1 1 Table 4-18 4.9.1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 0 0 0 0 0 0 0
0 0 1 1 0 0 1 1
-1.5 -11 -1.5 -11.0 -0.8 -5.5 -0.8 -5.5
10.5 10.5 7.9 7.9 5.3 5.3 4 4
3 -6.4 2.2 -7.3 1.5 -3.2 1.1 -3.6
5 5 3.8 3.8 2.5 2.5 1.9 1.9
PIP horizontal blanking timing Contrast, Brightness and Peak Level Adjustment
The peak level adjustment modifies the magnitude of each channel separately. It should be used to adapt once the signal levels to the following stage. The contrast adjustment influences all three channels and allows a further increase of 30% of the peak level magnitude. The effect of the brightness adjustment depends on the selected output mode (RGB/YUV). In YUV mode it changes the offset of the OUT2 (Y) signal only while in RGB mode it changes the offset of all three channels at the same time. The brightness increase is up to 20%. 4.9.2 Pedestal Level Adjustment
The pedestal level adjustment controlled by I2C signals BLKLR, BLKLG, BLKLB enables the correction of small offset errors, possibly appearing at the successive blanking stage of RGB processor. This adjustment has an effect on the setup level during the active line interval of each channel like the brightness adjustment but has an enhanced resolution of 0.5 LSB. The maximum possible offset amounts to 7.5 LSBs. In YUV mode (OUTFOR = '1') the action depends on the setting of BLKINVR and BLKINVB. If BLKINVR (BLKINVB) is active the offset applies to the blank level of the RV (BU) channel during the clamping interval for shifting the setup level to the negative direction. In RGB mode (OUTFOR = '0') BLKINVR and BLKINVB have no effect.
Micronas
4-32
SDA 9488X SDA 9588X
Preliminary Data Sheet System Description
YUV Mode BLKINVR = BLKINVB = 0 BLKINVR = BLKINVB = 1
BLKLR = 15 BLKLB = 15
BLKLR = 15 BLKLB = 15
32 BLKLR = 0 BLKLB = 0
32
BLKLR = 0 BLKLB = 0
RGB Mode
BLKLR = 15 BLKLB = 15 BLKLG = 15
0
BLKLR = 0 BLKLB = 0 BLKLG = 0
Figure 4-17 Pedestal level adjustment 4.10 Data Slicer
Depending on SERVICE, Closed Caption data ('Line 21') or WSS (Widescreen signalling) is sliced by the digital data slicer and can be read out from I2C interface. The line number of the sliced data is selectable with SELLNR. Therefore WSS and CC can be processed in different regions (e.g. CC with PAL M). The Closed Caption data is assumed to conform with the ITU standards EIA-608 and EIA-744-A. WSS data is assumed to conform with ETS 300 294 (2nd edition, May 1996). 4.10.1 Closed Caption
The closed caption data stream contains different data services. In field 1 (line 21) the captions CC1 and CC2 and the text pages T1 and T2 are transmitted whereas in field 2 (line 284) caption CC3, CC4, text T3, T4 and the XDS data are transmitted. For more information please refer to the above mentioned standards. Raw CC as well as prefiltered data is provided alternatively. With the built-in programmable XDS-Filter (XDSCLS), the program-rating information ('V-chip') as well Micronas 4-33
SDA 9488X SDA 9588X
Preliminary Data Sheet System Description
as others can be filtered out. The XDS filter reduce traffic on the I C bus and save calculation power of the main controller. If no class filter is selected, all incoming data 2 (both fields) is sliced and provided by the I C interface. When one or more class filters are chosen, only data in field 2 is sliced. Any combination of class filters is allowed. Each 'CLASS' is divided into 'TYPES' which can be sorted out by the XDS-secondary filter (XDSTPE). Any combination of type filter is allowed. Some type filter require an appropriate class filter. 4.10.2 Widescreen Signalling (WSS)
2
In WSS mode (SERVICE='1') no filtering is possible. All sliced data is passed to the output registers. In this case XDSTPE selects the field number of the data to be sliced. In Europe WSS carries for instance information about aspect ratio and movie mode. 4.10.3 Indication Of New Data
The sliced and possibly filtered data is available in DATAA and DATAB. The corresponding status bits are DATAV and SLFIELD. When new data were received, DATAV becomes '1' and the controller must read DATAA, DATAB and the status information. After both data bytes were read DATAV becomes '0' until new data arrives. It must be ensured that the data polling is activated once per field (16.7 or 20 ms) or every second field (33.3 or 40 ms), depending on the slicer configuration and inset field frequency. The field number of the data in DATAA and DATAB can be found in SLFIELD. If one or more XDS-class filter are activated, SLFIELD contains always '1'. Additionally pin 10 (INT) may flag that new data is received. Default this pin is in tri-state mode to be compatible with Micronas' SDA9388X/9389X PIP devices. It can also be configured by IRQCON to output a single short pulse when new data is available or behave equal to DATAV. In the last case the output remains active until the two data registers DATAA/DATAB are read. Both modes are useful to avoid continuos polling of the I2C bus. The micro-controller initiates I2C transfers only when required.
while (1){ i2c_read pip4_adr, status_reg_adr, status if (status & data_valid_mask) { i2c_read_inc pip4_adr, dataa_reg_adr, dataa, datab, status process_data dataa, datab, status } }
Figure 4-18 Example in pseudo-code for reading the data Micronas 4-34
SDA 9488X SDA 9588X
Preliminary Data Sheet System Description
4.10.4
Violence Protection
The rating information is sent in the program rating packet of the current (sometimes future) class in the XDS data stream. If only this information is desired the corresponding XDS filter (class 01h, type 05h) should be used to suppress other data. The class/packet bytes (0105h) precede the 2 bytes rating information. Each sequence is closed by the end-of-packet byte (0fh) and a checksum. This checksum complements the byte truncated sum of all bytes to 00h. Except comparison of the received rating with the adjusted user rating threshold the micro-controller should check the parity of each byte and validate the checksum to avoid miss-interpretation of wrong received data. The SDA 9488X/SDA 9588X offer some alternatives to blocking the PIP channel completely by switching it off (fig. (4-19)).
"Warning Message"
THIS PROGRAM CONTAINS VIOLENT SCENES
"Blue Screen"
"Mosaic"
Figure 4-19 Possibilities of PiP blocking The Mosaic mode (MOSAIC) hides details of the picture by reduced sharpness and increased aliasing. The picture looks scrambled and is less perceptible.
Micronas
4-35
SDA 9488X SDA 9588X
Preliminary Data Sheet Application Examples
5
Application Examples
The following two figures show 100/120Hz applications with the Micronas Featurebox SDA 9400/01. As the chip supports two I2C addresses and owns a RGB switch dual-PiP applications are easy to implement. The arrangement for best possible performance is shown in the fig. (5-1).
additional 1fH source
IN1-3
SDA9588X
SDA9588X
CVBS (Y/C, YUV)
SDA9588X
HSP/VSP OUT1-3 I2C +3.3V
SDA 9400
IN1-3
CVBS (Y/C, YUV)
SDA9588X
HSP/VSP OUT1-3 I2C
additional 2fH sources
CVBS (Y/C)
H/V1H
H/V2H
analog / digital Frontend
YUV1H
Featurebox i.e.SDA 9400
YUV2H
Backend i.e. SDA9380
Figure 5-1
SDA 9588X application with insertion in front of the Featurebox
The output of two 'OCTOPUS' are connected to the YUV (or RGB) input of the video processor of the main channel. Due to the 4:2:2 processing within the SDA 9400 the inset picture remains brilliant.
SDA9588X
CVBS (Y/C, YUV)
SDA9588X
HSP/VSP OUT1-3 I2C
SDA 9400
additional 2fH sources
CVBS (Y/C)
H/V1H
H/V2H
analog / digital Frontend
YUV1H
Featurebox i.e. SDA 9400
YUV2H
Backend i.e. SDA9380
Figure 5-2
SDA 9588X application with insertion behind the featurebox
Connecting of a SDA 9588X directly to the RGB input of the RGB processor is possible as well. One picture is generated from SDA 9588X device, the other one from the featurebox. This cheap implementation preserves the chroma of inset channel at its full bandwidth, although only field mode is possible for PiP picture. The output of an OSD/ Text processor may be fed to the RGB switch of the SDA 9588X. Micronas 5-36
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
6 6.1
I2C Bus I2C Bus Address Write Address1 Read Address1 1 1 1 1 0 0 1 1 0 0 1 1 1 1 0 1 (D6h) (D7h)
Table 6-1
Primary Address (pin 9='low-level') 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 1 (DEh) (DFh)
Write Address2 Read Address2 Table 6-2 6.2 WRITE READ
Secondary Address (pin 9 = 'high-level') I2C-Bus Format S 1101x110 A Subaddress A Data Byte A **** A P
S 1101x110 A Subaddress A Sr 1101x111 A Data Byte n NA P
S: Start condition / Sr Repeated start condition / A: Acknowledge / P: Stop condition / NA: No Acknowledge Write operation is possible at registers 00h-21h only, read operation is possible at registers 28, 2Ah-2Ch only. An automatic address increment function is implemented.
Micronas
6-37
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
6.3
I2C bus Command Table
Subadd (Hex) D7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h PIPON D6 CPOS1 D5 CPOS0 D4
Data Byte D3 READD D2 PROGEN D1 FIESEL1 D0 FIESEL0
YUVSEL
POSHOR7 POSHOR6 POSHOR5 POSHOR4 POSHOR3 POSHOR2 POSHOR1 POSHOR0 POSVER7 POSVER6 POSVER5 POSVER4 POSVER3 POSVER2 POSVER1 POSVER0 VFP3 VFP2 VFP1 FREEZE PIPBG1 VFP0 MOSAIC PIPBG0 HFP3 HFP2 HFP1 HFP0
DISPSTD1 DISPSTD0 FPSTD1 HSPINV FRSEL RGBINS1 FPSTD0 VSPINV INFRM RGBINS0
SIZEHOR1 SIZEHOR0 SIZEVER1 SIZEVER0 FMACTP VSPDEL3 FRWIDH1 HZOOM2 VSPDEL2 FRWIDH0 SELDEL2 CLPDEL2 AGCVAL1 HZOOM1 VSPDEL1 FRWIDV1 SELDEL1 CLPDEL1 AGCVAL0 HZOOM0 VSPDEL0 FRWIDV0 SELDEL0 CLPDEL0 NOSIGB LMOFST0 YCDEL0 CKILL0 CHRBW0 HUE0 SCADJ0 BLKLR0 BLKLG0 BLKLB0 PKLR0 PKLG0 PKLB0
VSPNSRQ VSPDEL4 VPSRED VERBLK FRWIDH2
SELDOWN SELDEL3 CLPDEL3 AGCVAL2
POSCOR DISPMOD1 DISPMOD0 CLPDEL4 AGCRES CVBSEL1 PLLITC1 CSTAND2 BGPOS IFCOMP1 SATNR CONADJ3 BRTADJ3 TRIOUT PKLR7 PKLG7 PKLB7 AGCMD1 CVBSEL0 PLLITC0 CSTAND1 SCMIDL0 IFCOMP0 FMACTI CONADJ2 BRTADJ2 REFINT PKLR6 PKLG6 PKLB6 AGCMD0 CLMPID1 NSRED1 CSTAND0 DEEMP1 HUE5 CPLLOF CONADJ1 BRTADJ1 BLKINVR PKLR5 PKLG5 PKLB5 AGCVAL3 CLMPID0 NSRED0 CSTDEX1 DEEMP0 HUE4 SCADJ4 CONADJ0 BRTADJ0 BLKINVB PKLR4 PKLG4 PKLB4
CLMPIST1 CLMPIST0 LMOFST1 YCDEL3 CSTDEX0 COLON HUE3 SCADJ3 BLKLR3 BLKLG3 BLKLB3 PKLR3 PKLG3 PKLB3 YCDEL2 LOCKSP ACCFIX HUE2 SCADJ2 BLKLR2 BLKLG2 BLKLB2 PKLR2 PKLG2 PKLB2 YCDEL1 CKILL1 CHRBW1 HUE1 SCADJ1 BLKLR1 BLKLG1 BLKLB1 PKLR1 PKLG1 PKLB1
Micronas
6-38
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
Subadd (Hex) D7 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 28h 2Ah 2Bh 2Ch MAT1 OUTFOR (reserved) SATADJ3 XDSCLS4 UVSEQ (reserved) D6 MAT0 UVPOLAR BGFRC SATADJ2 XDSCLS3 MPIPBG (reserved) D5 BGY1 BGU1 BGV1 SATADJ1 XDSCLS2 SERVICE (reserved) D4
Data Byte D3 FRY3 FRU3 FRV3 YPEAK2 XDSCLS0 SELLNR0 (reserved) D2 FRY2 FRU2 FRV2 YPEAK1 XDSTPE2 IRQCON2 PIPBLK D1 FRY1 FRU1 FRV1 YPEAK0 XDSTPE1 IRQCON1 PALIDL1 D0 FRY0 FRU0 FRV0 YCOR XDSTPE0 IRQCON0 PALIDL0
BGY0 BGU0 BGV0 SATADJ0 XDSCLS1 SELLNR1 (reserved)
POSOFV2 POSOFV1 POSOFV0 POSOFH4 POSOFH3 POSOFH2 POSOFH1 POSOFH0 (reserved) (reserved) (reserved) FRMMD DATAA7 DATAB7 (reserved) (reserved) (reserved) PIPSTAT DATAA6 DATAB6 (reserved) (reserved) (reserved) SYNCST1 DATAA5 DATAB5 DEVICE1 VSHRNK4 VSHRNK3 VSHRNK2 VSHRNK1 VSHRNK0 HSHRNK4 HSHRNK3 HSHRNK2 HSHRNK1 HSHRNK0 (reserved) SYNCST0 DATAA4 DATAB4 DEVICE0 (reserved) CKSTAT DATAA3 DATAB3 PRNSTD (reserved) STDET2 DATAA2 DATAB2 PALID CLPLEN1 STDET1 DATAA1 DATAB1 DATAV CLPLEN0 STDET0 DATAA0 DATAB0 SLFIELD
After power on the grey marked data bits are set to '1', all other to `0`.
Micronas
6-39
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
6.4
I2C Bus Command Description
Subaddress 00h PIPON D7 0 1 CPOS D6 0 0 1 1 D5 0 1 0 1 upper left position upper right position lower left position lower right position YUV Select select YUV mode CVBS or Y/C source YUV source Read Double Mode double read frequency for compatibility with systems that use 2fH (e.g.100 Hz, progressive) PIP display with single read frequency and 2x oversampling PIP display with double read frequency switches the PIP insertion on PIP insertion off PIP insertion on Coarse position coarse positioning of the picture PiP on
YUVSEL D4 0 1 READD D3 0 1
Micronas
6-40
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
PROGEN D2 0 1 FIESEL D1 0 0 1 1 D0 0 1 0 1
Progressive Scan Enable for compatibility with progressive scan systems each line of PIP is read once (normal operation) each line of PIP is read twice (line doubling operation) Field Select set field or frame display mode frame mode (if possible) field mode (first field only) field mode (second field only) field mode (one of both)
Subaddress 01h POSHOR D7-D0 Horizontal Picture Position horizontal position adjustment of the PIP in steps of 4 pixel shift direction depends on the coarse positioning of the picture
Subaddress 02h POSVER D7-D0 Vertical Picture Position vertical position adjustment of the PIP in steps of 1 lines shift direction depends on the coarse positioning of the picture
Micronas
6-41
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
Subaddress 03h HFP D7 1 D6 0 D5 0 D4 0 .. 0 0 0 1 VFP D3 1 0 0 D2 0 0 1 D1 0 0 1 D0 0 .. 0 .. 1 +7 lines, most right position 0 lines, nominal center position 0 1 0 .. 1 +14 pixel (0.7 s), most left position Vertical Fine Positioning changes the position of the vertical acquisition window by steps of 1 line -8 lines, most upper position of the image Note values refer to the undecimated picture 0 pixel, nominal center position Horizontal Fine Positioning changes the position of the horizontal acquisition window by steps of 2 pixel -16 pixel (-0.8 s), most right position of the image Note values refer to the undecimated picture
Subaddress 04h DISPSTD D7 0 0 1 1 D6 0 1 0 1 Display Standard selects the line standard of PIP display PIP depends on detected inset standard PIP display is always in 625 line mode PIP display is always in 525 line mode freeze last detected display standard and size
Micronas
6-42
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
FREEZE D5 0 1 MOSAIC D4 0 1 SIZEHOR D3 0 0 1 1 D2 0 1 0 1 horizontal decimation reduction = 2 reduction = 3 reduction = 4 reduction = 6 mosaic mode off mosaic mode on live picture still picture
Freeze Picture interrupts the inset picture writing and displays still picture
Mosaic Mode hides picture details, intended for use with parental control
Horizontal Size
SIZEVER D1 0 0 1 1 D0 0 1 0 1 vertical decimation reduction = 2 reduction = 3 reduction = 4 reduction = 6
Vertical Size
Micronas
6-43
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
Subaddress 05h FPSTD D7 0 0 1 1 D6 0 1 0 1 Force Parent Standard forces the parent standard to one of the following modes auto-detect parent standard 50Hz/625 lines parent standard forced 60Hz/525 lines parent standard forced freeze last detected standard PIP Background Display selects the background display PIP visible, no background display PIP invisible, background display in PIP PIP visible, full screen background display PIP invisible, background display in PIP and full screen background Frame Mode Activation Parent selects the parent condition for the activation of the frame mode Frame mode active for standard parent video sources only Frame mode active for some nonstandard sources also Horizontal Zoom D0 0 1 0 1 0 1 0 1 selects the parent (display) clock frequency 27.34 MHz 20.25 MHz 35.27 MHz 25.43 MHz 26.67 MHz 20.63 MHz 34.17MHz 28.04 MHz 6-44
PIPBG D5 0 0 1 1 D4 0 1 0 1
FMACTP D3 0 1 HZOOM D2 0 0 0 0 1 1 1 1 Micronas D1 0 0 1 1 0 0 1 1
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
Subaddress 06h HSPINV D7 0 1 VSPINV D6 0 1 VSPNSRQ D5 0 1 Horizontal Sync Pulse Inversion inverts the polarity of HSP no inversion, raising edge is sync reference HSP inverted, falling edge is sync reference Vertical Sync Pulse Inversion inverts the polarity of VSP no inversion, raising edge is sync reference VSP inverted, falling edge is sync reference Vertical Sync Pulse Noise Reduction activates automatic V insertion that generates vertical sync pulses in case of missing external VSP on off VSPDEL D4 0 1 D3 0 1 D2 0 1 D1 0 1 D0 0 ... 1 maximum delay, 4096 clocks of parent frequency Vertical Sync Pulse Delay delay of the vertical sync pulse in steps of 128 parent clocks no delay (0) Note delay depends on HZOOM
Subaddress 07h FRSEL D7 0 1 Micronas normal frame shaded frame with 3D impression 6-45 Frame Select selects between the normal frame and the shaded frame
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
INFRM D6 0 1 VPSRED D5 0 1 no reduction reduction on inner frame off inner frame on
Inner Frame activation actives inner frame (4 pix. width, 2 lines height) for displ. mode 2 and 3
Vertical Picture Size Reduction reduces vertical picture size to suppress black bars in 16:9 programs
FRWIDH D4 0 1 D3 0 1 D2 0 ... 1 7 pixel
Frame Width Horizontal adjusts the horizontal width of the PIP frame in steps of one pixel no horizontal frame
FRWIDV D1 0 1 D0 0 ... 1 3 lines no vertical frame
Frame Width Vertical adjusts the vertical width of the PIP frame in steps of one line
Subaddress 08h RGBINS D7 0 0 1 1 D6 0 1 0 1 RGB Insertion controls the insertion of external RGB/YUV sources no external insertion possible, FSW input inactive external insertion forced (FSW = 1) external insertion with FSW possible (priority of FSW input) external insertion with FSW possible (priority of PIP)
Micronas
6-46
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
VERBLK D5 0 1
Vertical Blanking switches the vertical blanking mode blanking level at DAC outputs only during line-blanking intervals blanking level at DAC outputs during line-blanking intervals and fieldblanking intervals, 16 lines following the parent vertical synchronization pulse are blanked
SELDOWN D4 0 1 SELDEL D3 1 0 0 D2 0 0 1 D1 0 0 1 D0 0 .. 0 .. 1 open source output TTL output
Select Down switches the driver type at the output of the SEL pin
Select Delay adjusts the delay of select signal -8 clock periods of display clock 0 clock periods of display clock +7 clock cycles of display clock
Subaddress 09h POSCOR D7 0 1 Position Correction activates correction of display position position correction disabled position correction enabled
Micronas
6-47
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
DISPMOD D6 0 0 1 1 D5 0 1 0 1 single PiP mode 3 x1/9 PiP (same content) 4 x1/16 PiP (same content) (reserved)
Display Mode selects display modes with equal pictures
CLPDEL D4 0 1 D3 0 1 D2 0 1 D1 0 1 D0 0 ... 1
Clamping Delay delay of the clamping pulse for the external RGB/YUV inputs in steps of 8 parent clock periods no delay (0) maximum delay, 256 clock periods of parent frequency
Subaddress 0Ah AGCRES D7 0 1 AGCMD D6 0 0 1 1 D5 0 1 0 1 controls the AGC operation evaluation of sync height and ADC overflow evaluation of sync height only evaluation of ADC overflow only AGC fixed (gain depends on AGCVAL) resets AGC normal operation reset of AGC AGC Mode Automatic Gain Control Reset
Micronas
6-48
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
AGCVAL D4 0 1 1 D3 0 0 1 D2 0 0 1 D1 0 .. 0 .. 1
Automatic Gain Control Value AGC value for fixed mode (AGCMD='11') input voltage 0.5 Vpp input voltage 1 Vpp input voltage 1.5 Vpp No Signal Behavior
NOSIGB D0 0 1 noisy picture colored background
controls behavior if synchronization is not possible (no source applied)
Subaddress 0Bh CVBSEL D7 0 0 1 1 D6 0 1 0 1 select CVBS source CVBS1 CVBS2 Y/C (Y@CVBS2 / C@CVBS3) CVBS3 Clamping Duration adjusts duration of clamping pulse for ADC (inset channel) 0.5s 0.9s 1.2s 1.5s CVBS Select
CLMPID D5 0 0 1 1 D4 0 1 0 1
Micronas
6-49
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
CLMPIST D3 0 0 1 1 D2 0 1 0 1 1.0s 1.5s 2.0s 2.5s
Clamping Pulse Start adjusts delay of clamping pulse for ADC refered to the horizontal sync
LMOFST D1 0 0 1 1 D0 0 1 0 1 no offset offset of 16 LSB offset of -8 LSB offset of -16 LSB
Luminance Offset modifies black to blank level offset
Subaddress 0Ch PLLITC D7 0 0 1 1 D6 0 1 0 1 VCR1 (very fast) VCR2 TV1 TV2 (very slow) Noise Reduction Inset PLL selects the level of noise reduction noise reduction disabled weak noise reduction heavy noise reduction medium noise reduction may cause trouble for VCR signals Note Inset PLL Time Constant switches the time constant of the inset PLL
NSRED D5 0 0 1 1 D4 0 1 0 1
Micronas
6-50
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
YCDEL D3 1 0 0 D2 0 0 1 D1 0 0 1 D0 0 .. 0 .. 1 +7 pixel (0.35 s) 0 pixel
Y/C Delay adjusts the delay between luminance and chrominance -8 pixel (-0.4 s with respect to undecimated picture)
Subaddress 0Dh CSTAND D7 0 0 0 0 1 1 1 1 D6 0 0 1 1 0 0 1 1 D5 0 1 0 1 0 1 0 1 Color Standard forces the desired color standard automatic standard identification NTSC-M PAL-N (Argentina) PAL-M NTSC44 PAL-B SECAM PAL60 Color Standard Exclusion excludes standards from automatic standard identification ignore PAL-M / PAL-N ignore SECAM, PAL B/G, PAL60, NTSC4.4 ignore PAL-M /PAL-N / NTSC-M ignore PAL-M / PAL-N / NTSC4.4 / PAL60 Standard Identification Speed sets the speed of the color standard recognition medium fast 6-51
CSTDEX D4 0 0 1 1 D3 0 1 0 1
LOCKSP D2 0 1 Micronas
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
CKILL D1 0 0 1 1 D0 0 1 0 1 -30 dB -18 dB -24 dB color always off
Color Killer Threshold damping of color carrier to switch color off Note only valid if color killer active (COLON='0'), values are approximative
Subaddress 0Eh BGPOS D7 0 1 SCMIDL D6 0 1 DEEMP D5 0 0 1 1 D4 0 1 0 1 Filter1 ITU recommendation Filter2 Filter3 Color On disable color killer color killer active color forced on default enhanced Deemphase Selection adjusts SECAM deemphase filter normal position 0.5 s delayed SECAM Identification Level changes SECAM identification sensitivity Burst Gate Position adjusts position of burst gate
COLON D3 0 1
Micronas
6-52
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
ACCFIX D2 0 1 CHRBW D1 0 0 1 1 D0 0 1 0 1 PAL wide medium reserved small ACC active
Disable Automatic Chroma Control disables the automatic chroma control (ACC) ACC fixed (ACC set to nominal value) Chroma Bandwidth SECAM small medium wide remark adjusts chroma bandwidth
Subaddress 0Fh IFCOMP D7 0 0 1 1 D6 0 1 0 1 no filtering chroma bandpass active IF-compensation bandpass (6dB/octave) reserved HUE D5 1 D4 0 D3 0 D2 0 D1 0 D0 0 .. 0 0 0 1 0 1 0 1 0 1 0 .. 1 43.4 skin color becomes redish 0 Hue Control phase of color subcarrier for NTSC -44.8 remark skin color becames greenish IF-Compensation Filter equalizes the IF-stage characteristic
Micronas
6-53
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
Subaddress 10h SATNR D7 0 1 FMACTI D6 0 1 CPLLOF D5 0 1 chroma PLL active chroma PLL opened (free running oscillator) SCADJ D4 0 0 1 D3 0 0 1 D2 0 1 1 D1 0 1 1 D0 0 ... 1 ... 1 max. positive deviation (+310 ppm) default (for nominal crystal frequency Color Subcarrier Adjustment color subcarrier frequency fine adjustment max. negative deviation (-150 ppm) disabled enabled Frame Mode Activation Inset sets the inset condition for the activation of the frame mode frame mode only active for standard inset video sources enhanced frame mode activation range Chroma PLL Off opens loop of chroma PLL (only for test and servicing) Satellite Noise Reduction stabilizes the horizontal PLL for bad satellite signals (fishes")
Subaddress 11h CONADJ D7 0 1 D6 0 1 D5 0 1 D4 0 .. 1 +30% contrast increase nominal contrast Contrast Adjustment adjusts the contrast of the picture, acts on OUT1-OUT3
Micronas
6-54
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
BLKLR D3 0 1 D2 0 1 D1 0 1 D0 0 .. 1 +7.5LSB offset
Blanking Level Red adjusts the pedestal level of the OUT1 channel in steps of 0.5LSB no pedestal
Subaddress 12h BRTADJ D7 D6 D5 D4 Brightness Adjustment adjusts the brightness of the picture, acts on OUT1-OUT3 in RGB mode (YUVFOR = '0') and on OUT1 in YUV mode (YUVFOR = '1') nominal brightness +20% brightness increase Blanking Level Green D0 0 .. 1 1 1 1 +7.5LSB offset adjusts the pedestal level of the OUT2 channel in steps of 0.5LSB no pedestal
0 1
0 1
0 1
0 .. 1
BLKLG D3 0 D2 0 D1 0
Subaddress 13h TRIOUT D7 0 1 Tristate Output sets OUT1-OUT3 to tristate mode (high resistance) normal operation, outputs are active pins OUT1-3 are in tri-state mode
Micronas
6-55
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
REFINT D6 0 1 BLKINVR D5 0 1 BLKINVB D4 0 1 normal refresh fast refresh
Refresh Intervall changes the refresh rate of eDRAM Note let it to this default value
Blanking Inversion Red inverts the sign of the OUT1 channel offset (BLKLR) offset added during the active picture offset added during blanking Blanking Inversion Blue inverts the sign of the OUT3 channel offset (BLKLB) offset added during the active picture offset added during blanking
BLKLB D3 0 1 D2 0 1 D1 0 1 D0 0 .. 1 +7.5LSB offset
Blanking Level Blue adjusts the pedestal level of the OUT3 channel in steps of 0.5LSB no pedestal
Micronas
6-56
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
Subaddress 14h PKLR D7 D6 D5 D4 D3 D2 D1 D0 Peak Level Red peak to peak output voltage of the OUT1 channel 0.3 Vpp 1 Vpp 1.2 Vpp Note
0 1 1
0 1 1
0 0 1
0 0 1
0 0 1
0 0 1
0 0 1
0 ... 0 ... 1
values refer to contrast (CONADJ) and brightness (BRTADJ) at minimum
Subaddress 15h PKLG D7 D6 D5 D4 D3 D2 D1 D0 Peak Level Green peak to peak output voltage of the OUT2 channel 0.3 Vpp 1 Vpp 1.2 Vpp Note
0 1 1
0 1 1
0 0 1
0 0 1
0 0 1
0 0 1
0 0 1
0 ... 0 ... 1
values refer to contrast (CONADJ) and brightness (BRTADJ) at minimum
Micronas
6-57
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
Subaddress 16h PKLB D7 D6 D5 D4 D3 D2 D1 D0 Peak Level Blue peak to peak output voltage of the OUT2 channel 0.3 Vpp 1 Vpp 1.2 Vpp Note
0 1 1
0 1 1
0 0 1
0 0 1
0 0 1
0 0 1
0 0 1
0 ... 0 ... 1
values refer to contrast (CONADJ) and brightness (BRTADJ) at minimum
Subaddress 17h MAT D7 0 0 1 1 BGY D5-D4 D6 0 1 0 1 EBU- Matrix NTSC-Japan Matrix NTSC-USA Matrix (reserved) Background Color Y adjusts the Y background color component the values gives the two MSBs of the Y background signal Frame Color Y adjusts the Y frame color component the value gives the 4 MSBs of the Y frame signal RGB Matrix Select selects the RGB matrix coefficients for YUV to RGB conversion
FRY D3-D0
Micronas
6-58
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
Subaddress 18h OUTFOR D7 0 1 UVPOLAR D6 0 1 BGU D5-D4 Output Format switches between RGB output and YUV output RGB output signals, matrix active YUV output signals UV Polarity switches between UV or inverted UV output, has no influence in RGB mode +U / +V output -U / -V output Background Color U adjusts the U background color component the values gives the two MSBs of the U background signal Frame Color U adjusts the U frame color component the value gives the 4 MSBs of the U frame signal
FRU D3-D0
Subaddress 19h BGFRC D6 0 1 BGV D5-D4 Background Frame Color selects background color table or frame color table for background color background color according to BGY, BGU, BGV background color according to FRY, FRU, FRV Background Color V adjusts the V background color component the values gives the two MSBs of the V background signal
Micronas
6-59
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
FRV D3-D0
Frame Color V adjusts the V frame color component the value gives the 4 MSBs of the V frame signal
Subaddress 1Ah SATADJ D7 0 1 1 D6 0 0 1 YPEAK D3 0 0 1 D2 0 1 1 YCOR D0 0 1 coring off 1LSB coring D1 0 1 1 no peaking recommended value strongest peaking Y Coring Enable suppresses noise introduced by peaking D5 0 0 1 D4 0 .. 0 .. 1 1.875 times saturation Y Peaking Adjustment adjusts luminance peaking nominal saturation no color Color Saturation Adjustment adjusts the color saturation in steps of x/8
Micronas
6-60
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
Subaddress 1Bh XDSCLS D7 0 1 X X X X D6 0 X 1 X X X XDSTPE D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 XDS-Secondary Filter Type all 05h 01h, 04h 40h 01h, 02h, 03h, 04h, 0Dh, 40h 01h, 04h, 05h 05h, 40h 01h, 02h, 03h, 04h, 05h, 0Dh, 40h D5 0 X X 1 X X D4 0 X X X 1 X D3 0 X X X X 1 XDS Class Select Closed Caption XDS-Primary Filter (Class) transparent, no filtering 'Current' class selected 'Future' class selected 'Channel' class selected 'Miscellaneous' class selected 'Public Services' class selected XDS Type Select Meaning no filtering program rating time information only out of band only VCR information time information and program rating out of band and program rating VCR information and program rating WSS field 0 1 0/1 0/1 0/1 0/1 0/1 0/1 Note behavior of these bits depends on selected dataservice
Subaddress 1Ch UVSEQ D7 0 1 U and V are correct U and V are exchanged UV Sequence changes the UV multiplex sequence (valid only if YUVSEL='1')
Micronas
6-61
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
MPIPBG D6 0 1 SERVICE D5 0 1 SELLNR D4 0 0 1 1 D3 0 1 0 1 IRQCON D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 Closed Caption black (8 IRE)
Multi-PIP Background selects the background color for multi-PIP mode same as background color Data Service Select selects data service for slicing Widescreen Signalling (WSS) Select Line Number line number of data service field 0 (field1) [NTSC] 20 (283), [PAL M] 17 (280) [NTSC] 21 (284), [PAL M] 18 (281) [PAL B/G] 22 (329) [PAL B/G] 23 (330) remark WSS Closed Caption Closed Caption WSS
Interrupt Request Pin Configuration output of INT pin is: tri-state (high-Z) interrupt, when new data received (pos. polarity) interrupt, when new data received (neg. polarity) equivalent to DATAV for both registers (pos. polarity) equivalent to DATAV for both registers (neg. polarity) inset V-pulse (50ns) inset field inset clamping pulse pulse length is 50ns high=first field, low = second field only for test purpose pulse length is approximately 2s remark
Micronas
6-62
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
Subaddress 1Dh PIPBLK D3 0 1 PALIDL D1 0 1 D0 0 .. 1 low rejection of PAL/NTSC no blank blanks the PIP PAL ID Level sensitivity of identification of PAL/NTSC signals high recjection of PAL/NTSC PIP Blank blanks the picture by setting it to background color
Subaddress 1Eh POSOFV D7 1 0 0 D6 0 0 1 D5 0 ... 0 ... 1 +12 lines Position Offset Horizontal D0 0 ... 0 0 0 1 0 1 0 1 0 ... 1 +240 pixel 0 pixel horizontal position offset in steps of 16 pixel -256 pixel 0 0 lines -16 lines Position Offset Vertical vertical position offset in steps of 4 lines
POSOFH D4 1 D3 0 D2 0 D1
Micronas
6-63
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
Subaddress 1Fh VSHRNK D4 0 D3 0 D2 0 D1 0 D0 0 ... 1 1 1 1 1 max. possible shrink Vertical Shrink changes the vertical size in steps of 2 lines no shrink, picture size according to SIZEVER Note max. usable value depends on SIZEVER
Subaddress 20h HSHRNK D4 0 D3 0 D2 0 D1 0 D0 0 ... 1 1 1 1 1 max. possible shrink Horizontal Shrink changes the horzontal size in steps of 4 pixel no shrink, picture size according to SIZEHOR Note max. usable value depends on SIZEVER
Subaddress 21h CLPLEN D1 D0 clamping pulse length 5us 3.75us 2.5us 1.25us Clamping Pulse Length Blanking Duration Note
0 0 1 1
0 1 0 1
10.5 us 7.9 us 5.2 us 2.6 us
the clamping pulse length and the blanking is also influenced by the setting of READD and HZOOM
Micronas
6-64
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
Subaddress 28h FRMMD D7 0 1 PIPSTAT D6 0 1 SYNCST D5 0 0 1 1 D4 0 1 0 1 locked to CVBS signal (60 Hz) locked to CVBS signal (50 Hz) Color Killer Status chroma is off on PIP off PIP on Inset Synchronization Status inset synchronization PLL is not locked to CVBS signal Frame Mode Indication PIP displays field or frame mode field mode, one field is repeated twice frame mode, both fields are displayed PIP Status indication of visibility of PIP, corresponds to PIPON
CKSTAT D3 0 1
Micronas
6-65
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
STDET D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1
Standard Detection detected color standard nonstandard or standard not detected NTSC-M PAL-M NTSC44 PAL60 PAL-N SECAM PAL-B/G
Subaddress 2Ah DATAA D7-D0 First Data Byte first word of sliced data, D7 = MSB, D0 = LSB
Subaddress 2Bh DATAB D7-D0 Second Data Byte second word of sliced data, D7 = MSB, D0 = LSB
Subaddress 2Ch DEVICE D5 0 0 1 1 D4 0 1 0 1 PIP IC SDA 9488X (PIP IV Basic) SDA 9489X (PIP IV Advanced) SDA 9588X (OCTOPUS) SDA 9589X (SOPHISTIUS) Device Identification
Micronas
6-66
SDA 9488X SDA 9588X
Preliminary Data Sheet I2C Bus
PRNSTD D3 0 1
Parent Standard Detection status of parent (display) standard detection 60Hz field frequency detected 50Hz field frequency detected
PALID D2 0 1 NTSC signal PAL signal
PAL Identification identification of PAL signal Note not valid if STDET= '000'
DATAV D1 0 1 SLFIELD D0 0 1 first field second field
Data Valid new data indication, used for data flow control (polling mode) data read via I2C or no data available new data received and available in DATAA and DATAB Sliced Data Field Number DATAA and DATAB are from
Micronas
6-67
SDA 9488X SDA 9588X
Preliminary Data Sheet Pin Description
7 pin 1 (XIN) 2 (XQ)
Pin Description schematic
VDD VDD VDD
remark crystal oscillator, input can be used for external clocking
XQ
XIN
3 (HSP) 4 (VSP)
H SP VSP
VD D
schmitt-trigger input with high hysteresis, for best jitter performance use pulses with steep slopes
5 (SDA) 6 (SCL)
SDA SCL
VDD
low-side driver not used for SCL, slope of acknowledge is limited
slope contr ol
9 (I2C)
I2C
VDD
I2C address selection, only static switch supported
Micronas
7-68
SDA 9488X SDA 9588X
Preliminary Data Sheet Pin Description
pin 10 (INT)
schematic
VDD
remark
INT
11 (IN1) 12 (IN2) 13 (IN3)
VDD IN1 IN2 IN3
clamped RGB/YUV video inputs, if not used let open or connect with 10nF to ground
+V CL -
14 (FSW)
FSW
VDD
fast switch input
15 (SEL)
VDD
SEL
low-side driver can be disabled (open source mode)
Micronas
7-69
SDA 9488X SDA 9588X
Preliminary Data Sheet Pin Description
pin 16 (OUT3) 17 (OUT2) 18 (OUT1)
+ -
schematic
VD D O UT1 O UT2 O UT3
remark RGB/YUV video outputs
21 (VREFH) 25 (VREFL) 27 (VREFM)
VDD
VDD VREFM
VDD
reference voltage for ADC and DAC
VREFL
VREFH
24 (CVBS3) 26 (CVBS2) 28 (CVBS1)
VDD VDD CVBS1 CVBS2 CVBS3
clamped video inputs
Micronas
7-70
SDA 9488X SDA 9588X
Preliminary Data Sheet Absolute Maximum Ratings
8
Absolute Maximum Ratings Parameter Ambient Temperature Storage Temperature Junction Temperature Soldering Temperature Input Voltage Symbol TA Tstg Tj Tsold Vi Vi Output Voltage Supply Voltages VQ VQ VDD Ptot ILU VESD,HBM -100 -2000 -0.3V -0.3 -0.3V -0.3 -0.3 -0.25 Limit Values min. 0 -55 max. 70 125 125 260 VDD+0.3V 5.5 VDD+0.3V 5.5 3.6 0.25 0.86 100 2000 C C C C 1 V 1 V V V W mA V HBM: 1.5k, 100pF duration <10s except SDA, SCL, HSP, VSP SDA, SCL, HSP, VSP only except SDA SDA only Unit remark
Supply Voltage Differentials Total Power Dissipation Latch-Up Protection ESD robustness
All voltages listed are referenced to ground (0V, VSS) except where noted. Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit.
Micronas
8-71
SDA 9488X SDA 9588X
Preliminary Data Sheet Recommended Operating Range
9
Recommended Operating Range Parameter Supply Voltages Ambient Temperature HSP Signal Frequency HSP Signal Frequency HSP Signal Frequency HSP Signal Rise Time HSP Signal High Time HSP Signal Low Time VSP Signal Frequency VSP Signal Frequency VSP Signal High Time VSP Signal Low Time Horizontal Frequency Horizontal Frequency Amplitude of synchronization pulse length of horizontal synchronization puls length of vertical synchronization puls chroma amplitude Input Coupling Capacitors CVBS Source Resistance Symbol min. VDDxx TA fPH fP2H fP2H tr tHH tLH fPV fPV tHV tLV fH fH Vsync tDH tDV ACHR CCLI 2.2 200 200 15.734 15.625 300 4.7 22 300 10 100 200 900 50/60 100/120 3.15 0 15.000 30.000 11.7 Limit Values typ. 3.3 25 15.625 31.250 25.2 max. 3.45 70 16.250 32.500 48 100 V C kHz kHz kHz ns ns ns Hz Hz ns ns kHz kHz mV s s mV nF burst necessary for proper clamping 60 Hz input 50 Hz input scan rate conversion 1fH mode 2fH mode VGA mode noisefree transition Unit Remark
Main horizontal / vertical Sync Inputs: VSP, HSP
Inset Input: CVBS1, CVBS2, CVBS3
RSRCI
100
500
Micronas
9-72
SDA 9488X SDA 9588X
Preliminary Data Sheet Recommended Operating Range
Parameter Input Voltage Range at inputs CVBS1-3 Reference Voltage Low Reference Voltage Middle Reference Voltage High
Symbol min. Vi 0.5
Limit Values typ. 1 max. 1.5
Unit V
Remark dep. on AGC setting
Reference Voltages:VREFL, VREFM, VREFH VREFL VREFM VREFH 1.05 1.81 3.15 1.11 1.91 3.3 1.17 2.00 VDDA1 V V V
RGB/YUV Switch:IN1,IN2,IN3,FSW Input Coupling Capacitors Source Resistance Input Voltage Range at inputs IN1-3 Input Voltage Range at inputs FSW IC Address: I2C Input Voltage Range for Address Input Voltage Range for Address VSA1 VSA2 0 2.8 0.8 VDDD V V CCLS 2.2 10 100 nF necessary for proper clamping
RSRCS VIS VIF 0.3 0.3
100 1 1
500 1.6 1.6
V V
Fast IC Bus (All values are referred to min(VIH) and max(VIL)) This specification of the bus lines need not be identical with the I/O stages specification because of optional series resistors between bus lines and I/O pins. SCL Clock Frequency Inactive Time Before Start Of Transmission Set-Up Time Start Condition Hold Time Start Condition SCL Low Time Micronas fSCL tBUF tSU;STA tHD;STA tLOW 0 1.3 0.6 0.6 1.3 9-73 400 kHz s s s s
SDA 9488X SDA 9588X
Preliminary Data Sheet Recommended Operating Range
Parameter SCL High Time Set-Up Time DATA Hold Time DATA SDA/SCL Rise/Fall Times Set-Up Time Stop Condition Capacitive Load/Bus Line High-Level Input Voltage Low-Level Input Voltage Spike Duration At Inputs Low-Level Output Current Load resistance Load capacitance Frequency
Symbol min. tHIGH tSU;DAT tHD;DAT tR, tF tSU;STO Cb VIH VIL 3V -0.25V 0 IOL 0.6 100 0 20+$ 0.6
Limit Values typ. max.
Unit s ns 0.9 300 s ns s 400 5.5V 1.5 pF 1 V ns mA
Remark
$=0.1Cb/pF
IC Bus Inputs/Output: SDA, SCL also for SDA/SCL input stages
0
50 6
Digital To Analog Converters (7-bit):OUT1, OUT2, OUT3 RL CL fxtal 20.248 20.25 10 30 20.252 k pF MHz deviation outside this range will cause color decoding failures deviation outside this range will cause color decoding failures
Crystal Specification: XIN, XQ
Maximum Permissible Frequency Deviation
fmax/ fxtal
-100
100
10-6
Recommended Permissible Frequency Deviation Micronas
f/fxtal
-40
0
40
10-6
9-74
SDA 9488X SDA 9588X
Preliminary Data Sheet Recommended Operating Range
Parameter Load Capacitance Series resonance resistance Motional capacitance Parallel capacitance
Symbol min. CL RS C1 C0 12
Limit Values typ. 27 25 27 7 max. 39
Unit pF fF pF
Remark
In the operating range the functions given in the circuit description are fulfilled.
Micronas
9-75
SDA 9488X SDA 9588X
Preliminary Data Sheet Characteristics
10
Characteristics
(Assuming Recommended Operating Conditions) Parameter Average total supply current All Digital Inputs (TTL, IC) Input Capacitance Input Leakage Current CI -10 7 10 pF A incl. leakage current of SDA output stage IOH=-200A IOH=-4.5mA IOL=1.6mA, only valid if bit SELDOWN= 1 Symbol min. IDDtot 180 Limit Values typ. 210 max. 240 mA Unit Remark
SEL High-Level Output Voltage High-Level Output Voltage Low-Level Output Voltage VOH VOH VOL 2.4 V 1.5V VDD VDD 0.4 V V V
FSW Low-Level Input Voltage High-Level Input Voltage Delay FSW in -> SEL out IC Inputs: SDA/SCL Schmitt Trigger Hysteresis Low-Level Output Voltage Low-Level Output Voltage Vhys 0.1 0.2 0.5 V not tested VIL VIH -0.25 0.9 10 0.4 VDD+0.5 V V ns
IC Input / Output: SDA (Referenced to SCL; Open Drain Output) VOL VOL 0.4 0.6 V V IOL=3mA IOL=max
Micronas
10-76
SDA 9488X SDA 9588X
Preliminary Data Sheet Characteristics
Parameter Output Fall Time from min(VIH) to max(VIL) CVBS Input Leakage Current CVBS Input Capacitance Input Clamping Error Input Clamping Current
Symbol min. tOF
Limit Values typ. max. 250 20+0.1* Cb /pF -100 7 -1 43 1 326
Unit ns
Remark 10pFCb40 0pF clamping inactive
Analog Inputs CVBS1, CVBS2, CVBS3 IL CI CLE |ICLP| 100 nA pF LSB settled state A dependent on clamping error
max. Input Clamping Current deviation Reference Voltage Difference D.C. Differential Nonlinearity Crosstalk between CVBS Inputs D.C. Differential Nonlinearity Full Range Output Voltage
|ICLPx|/ |ICLP| VREFHVREFL DNL CT
-40 0.5 -1 -50
40 1.5 1
% V LSB dB VDDA1=3.3 V VREFH-VREFL = max
Digital To Analog Converters (7-bit): Outputs OUT1, OUT2, OUT3 DNLE VOL -0.5 0.3 0.5 LSB V CON, UAMP, VAMP, YAMP = 0 CON, UAMP, VAMP, YAMP = max
Full Range Output Voltage
VOH
1.6
V
Micronas
10-77
SDA 9488X SDA 9588X
Preliminary Data Sheet Characteristics
Parameter Output Voltage
Symbol min. VO 0.9
Limit Values typ. 1 max. 1.1
Unit V
Remark CON, UAMP, VAMP, YAMP = default, VREF = const.
Deviation of OUT1-3 (matching) Contrast Increase Output Amplitude Ratio (UOH-UOL)/UOL Brightness Increase Pedestal Level variation Input Voltage Range Bandwith (-3dB) Gain Gain Difference RGB Crosstalk Between Inputs Isolation (off state) Clamping Level Difference at Output
MCH CON AMP BRT PED VI BW G G CTI D CLPE
-3 30 400
3
% % %
15 +/- 7.5 1.2 25 0.9 1.1 3 -45 45 15
LSB LSB Vpp MHz RL>10k; CL=20pF f<4MHz f=5MHz, (Y-UV) f=5MHz between external and internal source VCR1 and VCR2 TV1 and TV2
RGB / YUV switch; IN1, IN2, IN3
% dB dB mV
Colordecoder/Synchronization and Luminance Processing Horizontal PLL pull-inrange Horizontal PLL pull-inrange fHf/fH fHf/fH 13.3 13.3 17.4 17.4 kHz kHz
Micronas
10-78
SDA 9488X SDA 9588X
Preliminary Data Sheet Characteristics
Parameter Amplitude of synchronization pulse length of horizontal synchronization pulse length of vertical synchronization pulse ACC range AGC range Chroma PLL pull-inrange Data slicer Data level Data height Eye Height Co Channel Distortion Co Channel Distortion Max. permissible Noise
Symbol min. Vsync 60
Limit Values typ. max. 600
Unit mV
Remark AGC set to 1.2 V input signals
tDH tDV CRACC CRAGC fSC
1.8 22 -24 -7.5 +/- 500 +6 +2
s s dB dB Hz nominal crystal frequency CC CC 25kHz 50kHz
VD VD EH CD25 CD50 N
266 280 26.6
350 350
434 420 174 155 20
mV mV % mV mV dB
The listed characteristics are ensured over the operating range of the integratd circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage.
Micronas
10-79
SDA 9488X SDA 9588X
Preliminary Data Sheet Diagrams
11
Diagrams
Figure 11-1 Displaymode 0 with picture sizes 1/9 and 1/16
Figure 11-2 Displaymode 0 with picture size 1/36 and with scaling
Micronas
11-80
SDA 9488X SDA 9588X
Preliminary Data Sheet Diagrams
0
0
1
1
2 3
2
Figure 11-3 Display mode 2 (3 pictures with same content) and Display mode 3 (4 pictures with same content)
Micronas
11-81
SDA 9488X SDA 9588X
Preliminary Data Sheet Diagrams
Teletext or OSD processor optional 2 n d PIP R G B FSW
TUNER1
CVBS 1 CVBS 2 CVBS 3
SEL R(V) G (Y) B(U)
RGB Processor
Y U V
SEL R(V) G (Y) B(U)
R G B
HSP VSP CVBS 1
TUNER2
Main Channel Decoder & Sync
Figure 11-4 General Application with 3 CVBS sources and Teletext-Processor
Teletext or OSD processor optional 2 n d PIP R G B FSW
Y, U, V
RGB Processor
Y U V
R G B
HSP VSP CVBS 1
TUNER2
Main Channel Decoder & Sync
Figure 11-5 General Application with YUV source from DVD
Micronas
11-82
SDA 9488X SDA 9588X
Preliminary Data Sheet Diagrams
10 0 gain [dB] 10 20 30 40
1/9 PiP
3 6
10 0 gain [dB] 10 20 30 40
1/16 PiP
3 6
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
frequency [MHz]
frequency [MHz]
YPEAK = '010' YPEAK = '100' YPEAK = '111'
10 0 gain [dB] 10 20 30 40
YPEAK = '010' YPEAK = '100' YPEAK = '111'
3 6
1/36 PiP
0
1
2
3
4
5
6
7
8
9
10
frequency [MHz]
YPEAK = '010' YPEAK = '100' YPEAK = '111'
Figure 11-6 Characteristic (PAL) of luminance decimation filter for different peaking factors
Micronas
11-83
SDA 9488X SDA 9588X
Preliminary Data Sheet Diagrams
10 0 gain [dB] 10 20 30 40
1/9 PiP
3 6 gain [dB]
10 0 10 20 30 40
1/16 PiP
3 6
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
frequency [MHz]
frequency [MHz]
YPEAK = '010' YPEAK = '100' YPEAK = '111'
10 0 gain [dB] 10 20 30 40
YPEAK = '010' YPEAK = '100' YPEAK = '111'
3 6
1/36 PiP
0
1
2
3
4
5
6
7
8
9
10
frequency [MHz]
YPEAK = '010' YPEAK = '100' YPEAK = '111'
Figure 11-7 Characteristic (NTSC) of luminance decimation filter for different peaking factors
Micronas
11-84
SDA 9488X SDA 9588X
Preliminary Data Sheet Diagrams
10
10
0
3 6 gain [dB]
0
3 6
gain [dB]
10
10
20
20
30
30
40
0
0.25
0.5
0.75
1 1.25 1.5 frequency [MHz]
1.75
2
2.25
2.5
40
0
0.25
0.5
0.75
1 1.25 1.5 frequency [MHz]
1.75
2
2.25
2.5
1/9 PiP 1/16 PiP 1/36 PiP
1/9 PiP 1/16 PiP 1/36 PiP
10
0
3 6
gain [dB]
10
20
30
40
0
0.25
0.5
0.75
1 1.25 1.5 frequency [MHz]
1.75
2
2.25
2.5
1/9 PiP 1/16 PiP 1/36 PiP
Figure 11-8 Characteristic of chrominance decoder filter (small, medium and narrow)
Micronas
11-85
SDA 9488X SDA 9588X
Preliminary Data Sheet Application Circuit
12
Application Circuit
Y U V
or
CVBS1 Y C
or
CVBS1 CVBS2 CVBS3
R6 75
C18 10n C19 10n C20 10n R7 75 R8 75
C1 * 27p X1 20.25 MHz
C8 10n
C2 * 27p
1 2 3 4
XIN XQ HSP VSP
CVBS1 VREFM CVBS2 VREFL
28 27 26 25 24 23 22 21 20 19 18 17 16 15
C9 1
HP VP SDA SCL
+3.3V
L1 10 C3 10 R1 100 R2 100
C10 10n C11 1 C12 10n C13 10
L2 10
+3.3V
SDA9588X
5 6 7
C4 10n
SDA SCL VDD VSS I2C INT IN1 IN2 IN3 FSW
CVBS3 VSSA1 VDDA1 VREFH VSSA2 VDDA2 OUT1 OUT2 OUT3 SEL
L3 10 C14 10n C15 1
+3.3V
+3.3V J1 DEh D6h
8 9 10 11
I2C Address
C5 10n C6 10n C7 10n
C16 10n
C17 10
RVIN GYIN BUIN FSW
R3 75
12 13 14
RVOUT GYOUT BUOUT SEL INT
R4 75
R5 75
*) exact value depends on crystal specification
Micronas
12-86
SDA 9488X, SDA 9588X
PRELIMINARY DATA SHEET
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-561-1PD
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
87
Micronas

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